• qprimed@lemmy.ml
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    22 hours ago

    and, honestly, RISC-V is the right place to spend it. RISC has super powers.

    • morrowind@lemmy.ml
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      22 hours ago

      What do you mean by that. RISC-V is open source but it doesn’t have “superpowers” that I know of?

      • qprimed@lemmy.ml
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        22 hours ago

        “reduced” is the super power. I would much rather put the smarts into the assembler/compiler/interpreter than the silicon. have been followed RISC since the 80’s and discovered that I am really a RISC guy living in CISC world. open arch is the world dominating cherry-on-top.

        • Alex@lemmy.ml
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          15 hours ago

          That’s not really true. Yes avoiding complex instructions makes the front end easier to pipeline but there are lots of smarts in the backend to do prediction and scheduling to keep the execution units fed. The ISA might be free to use but no one is sharing their highly optimised server silicon architecture designs.

          RISC-V’s challenge is can they standardise the software ecosystem enough that things just work across a multitude of chip providers or does everything devolve into specialist distributions taking advantage of each manufacturers “special sauce” custom instructions.

          Gaining design wins over Arm’s microcontrollers for bespoke hardware was the easy bit. Replacing stuff in the server space is much harder and something that took Arm decades to make inroads into.

          • qprimed@lemmy.ml
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            11 hours ago

            great reply. I am not saying RISC is the panecea, what I am saying is that there are more options for workload optimization further up the stack and rebalancing of the intelligence from the silicon to the software is an advantage.

            some time ago most CISC core design become more RISC-y and, to indulge in some ISA snobbery, I just want to slash and burn the CISC presentation to the software layer. memory is cheap, bus bandwidth is insane - simplification on the ISA just seems like a hardware complexity win all around and I am willing to pay for that in compiler complexity that incorporates changes more easily than hardware or CISC microcode.

            RISC-V’s challenge is can they standardise the software ecosystem enough[…]

            agreed. this is why I say my wait may be coming to an end.

            personally, I think RISC is the more flexible design in almost every usecase. cycle for cycle, RISC hits the right buttons for me across the widest number of situations once we get above the “magic hardware” layer. willing to flog the CISC vs RiSC horse convo if you have recent information, and thanks for the response.

          • qprimed@lemmy.ml
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            11 hours ago

            meh (not dismissive - just cute), ecosystem mootness is overrated. at the heart of every CISC beats a RISC. strip away the mask and lets poke the nuclear core.

        • masterspace@lemmy.ca
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          20 hours ago

          Do you have any resources by any chance that explain the difference well?

          I work in high level software, so understand the benefit of doing things at ide time vs compile time vs runtime, and I’ve coded in assembly back in the day and understand instruction sets at a very rough level, but I’m not really familiar with specifically what differentiates RISC / ARM / x64, or why RISC’s reductions would be good / bad / what trade-offs come with them.

          • qprimed@lemmy.ml
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            11 hours ago

            CPI per CPI… RISC, but thats a trap of a question and you know it ;-)

            tons of variables in that question, but there should be more headroom in RISC designs and thats why, internally, most things are RISC-y.

              • qprimed@lemmy.ml
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                8 hours ago

                ok. my apologizes.

                there really are tons of things to consider with that question. RISC has historically allowed for faster clocking and fewer cycles per instruction, so thats a win. RISC also requires more instructions per useful operation and also blows up the binary size, so… :-(

                all things being equal (hahaha) RISC has more headroom and legroom for future improvements that dont complecate the silicon to extreme degrees. the vast majority of CISC designs are now pretty RISC-like at their cores, but the software interface remains CISC and, I think, complicates and limits variety and advancement.

                imho, a properly spec’d RISC processor and a carefully designed compiler, cycle for cycle, macro for macro and watt for watt outperforms a CISC design (even with a RISC-like core). major computing holy wars are been waged over this for decades.

                all I currently have access to are older studies that show mixed general purpose results on RISC vs CISC (performance, not power efficiency), but if I had to make a choice about what my future ideal processor would be, it would be RISC core and RISC instruction set architecture simply due to less complexity, more efficient use of wafer space and lower power requirements. then we start talking about massively parallel RISC in tiny spaces and, for many (but not all) workloads, thats a big win.

      • InverseParallax@lemmy.world
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        20 hours ago

        It’ll get there quick.

        I worked on HPC cpus, scaling up isn’t that hard, the hard part is dealing with your Isa baggage.